1. Field of the Invention
The present invention relates to a comparator with offset compensation, in particular for analog digital converters (ADCs) operating by successive approximations (ADC SAR—Analog Digital Converter Successive Approximation Register).
2. Discussion of the Related Art
As is known, precision is an important requirement for comparators; techniques ensuring a reliable correction of the existing offset due to the mismatch among physical components forming the converter are therefore required.
Several solutions have been suggested for correction of the offset.
A first solution, shown in FIG. 1 and disclosed in B. Razavi, B. Wooley “Design Techniques for High-Speed, High-Resolution Comparators”, IEEE Journal of Solid-State VOL. M7, N. 12, December 1992, comprises N preamplifier stages 1 upstream of a latch 2 having an offset. The offset of preamplifiers 1 is detected in an initial autozeroing step, by shorting the inputs of preamplifiers 1 at a preset voltage and sampling the outputs of preamplifiers 1. Thereby, the offset of latch 2 is reduced, as it is divided by the product of the gains of preamplifiers 1 (1/(G1* . . . Gi* . . . *GN), Gi representing the gain of a generic preamplifier 1. Preamplifier stages 1 are generally low-gain (˜2-3) in order to have a good band/consumption ratio. Accordingly, in order to sufficiently reduce the offset of latch 2, a certain number of preamplifier stages needs to be provided, thereby the overall comparison time is rather long and depends on the desired level of reduction of the offset. Furthermore, the circuit has a considerable bulk and a high power consumption.
Another solution, shown in FIG. 2 and disclosed in N. Verma, A. Chandrakasan “An Ultra Low Energy 12-bit Rate-Resolution Scalable SAR ADC for Wireless Sensor Nodes”, IEEE Journal of Solid-State VOL. 42, N. 6, June 2007, uses a latched comparator with a single offset cancellation in the autozeroing step at the beginning of conversion, thus eliminating the need to perform the resampling of the offset after each comparison. Namely, transistors 3 and 4, operating as current sources, are biased so that input transistors 1, 2 have the same source voltages (VS1=VS2) when receiving identical input signals VIN. This solution requires a rather complicated auxiliary circuitry for managing the different control steps, with a subsequent impact on the occupied area. Furthermore, the presence of local feedbacks leads to problems in the stability of the circuit in critical conditions.
A further solution, shown in FIG. 3 and disclosed in T. Shima, K. Miyoshi “Simple and Accurate Comparator Circuit”, IEEE Circuits and Systems VOL. 1, August 2002, uses a latched comparator with offset cancellation at each comparison. This circuit is based on the storing, on capacitor C connected between the gate terminals of two transistors 5 and 6, of the difference in gate-source voltage of two transistors 5, 6 in the absence of a signal. Thereby, in the subsequent comparing step and then in the step latching, the output signal is independent of the offset. This solution has a less complicated structure than the previous one with respect to the auxiliary circuitry, but requires the inputs to be shorted before each comparison as the stored offset is lost after the comparison.
It is an object of the present invention to provide a comparator overcoming the drawbacks of the prior art.